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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4049B buffers HEX inverting buffers Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEX inverting buffers DESCRIPTION The HEF4049B provides six inverting buffers with high current output capability suitable for driving TTL or high capacitive loads. Since input voltages in excess of the buffers' supply voltage are permitted, the buffers may also be used to convert logic levels of up to 15 V to standard TTL levels. Their guaranteed fan-out into common bipolar logic elements is shown in the table below. HEF4049B buffers HEF4049BP(N): 16-lead DIL; plastic (SOT38-1) HEF4049BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF4049BT(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America Guaranteed fan-out in common logic families DRIVEN ELEMENT standard TTL 74 LS 74 L GUARANTEED FAN-OUT 2 9 16 Fig.3 Logic diagram (one gate). APPLICATION INFORMATION Some examples of applications for the HEF4049B are: * LOCMOS to DTL/TTL converter * HIGH sink current for driving 2 TTL loads Fig.1 Functional diagram. * HIGH-to-LOW level logic conversion Input protection Fig.4 Input protection circuit that allows input voltages in excess of VDD. Fig.2 Pinning diagram. FAMILY DATA, IDD LIMITS category BUFFERS See Family Specifications January 1995 2 Philips Semiconductors Product specification HEX inverting buffers DC CHARACTERISTICS VSS = 0 V; VI = VSS or VDD HEF VDD V VO V SYMBOL MIN. Output (sink) current LOW Output (source) current HIGH Output (source) current HIGH 5 2,5 IOH 1,7 - 1,4 - 4,75 10 15 5 10 15 0,4 0,5 1,5 4,6 9,5 13,5 IOH IOL 3,5 12,0 24,0 0,52 1,3 3,6 Tamb (C) -40 MAX. - - - - - - +25 MIN. 2,9 10,0 20,0 0,44 1,1 3,0 MAX. - - - - - - HEF4049B buffers +85 MN. 2,3 8,0 16,0 0,36 0,9 2,4 1,1 MAX. - - - - - - - mA mA mA mA mA mA mA HEC VDD V VO V SYMBOL MIN. Tamb (C) -55 MAX. - - - - - - +25 MIN. 2,9 10,0 20,0 0,44 1,1 3,0 MAX. - - - - - - +125 MIN. 1,9 6,7 13,0 0,36 0,9 2,4 MAX. - - - - - - mA mA mA mA mA mA Output (sink) current LOW Output (source) current HIGH 4,75 10 15 5 10 15 0,4 0,5 1,5 4,6 9,5 13,5 IOH IOL 3,6 12,5 25,0 0,52 1,3 3,6 VDD V Propagation delays In On HIGH to LOW LOW to HIGH Output transition times HIGH to LOW LOW to HIGH 5 10 15 5 10 15 5 10 15 5 10 15 SYMBOL TYP. 35 MAX. 70 30 25 100 50 40 40 20 14 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns TYPICAL EXTRAPOLATION FORMULA 26 ns + (0,18 ns/pF) CL 11 ns + (0,08 ns/pF) CL 9 ns + (0,05 ns/pF) CL 23 ns + (0,55 ns/pF) CL 14 ns + (0,23 ns/pF) CL 12 ns + (0,16 ns/pF) CL 3 ns + (0,35 ns/pF) CL 3 ns + (0,14 ns/pF) CL 2 ns + (0,09 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL tPHL 15 12 50 tPLH 25 20 20 tTHL 10 7 60 tTLH 30 20 January 1995 3 Philips Semiconductors Product specification HEX inverting buffers HEF4049B buffers VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (W) 2 500 fi + (foCL) x VDD2 11 000 fi + (foCL) x VDD 35 000 fi + (foCL) x 2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V) VDD2 January 1995 4 |
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